Cortex-A53
| Designed by | ARM Holdings |
|---|---|
| Microarchitecture | ARMv8-A |
| Cores | 1–4 per cluster |
| L1 cache | 8–64 KB |
| L2 cache | 128 KB–2 MB |
The ARM Cortex-A53 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A53 is a superscalar processor capable of dual-issuing some instructions. It is available as SIP core to licensees, and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration.
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