OpenRISC 1200

The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].

A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken over by the Free and Open Source Silicon Foundation at the librecores.org website. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).

The IP core of the OR1200 is implemented in the Verilog HDL. As an open source core, the design is fully public and may be downloaded and modified by any individual. The official implementation is maintained by developers at OpenCores.org. The implementation specifies a power management unit, debug unit, tick timer, programmable interrupt controller (PIC), central processing unit (CPU), and memory management hardware. Peripheral systems and a memory subsystem may be added using the processor's implementation of a standardized 32-bit Wishbone bus interface. The OR1200 is intended to have a performance comparable to an ARM10 processor architecture.

The OR1200 CPU is an implementation of the 32-bit ORBIS32 instruction set architecture (ISA) and (optionally) ORFP32X ISA implementing IEEE-754 compliant single precision floating point support. The ISA has five instruction formats and supports two addressing modes: register indirect with displacement, and PC-relative. The implementation has a single-issue 5-stage pipeline and is capable of single cycle execution on most instructions. The CPU also contains a MAC unit in order to better support digital signal processing (DSP) applications.

...
Wikipedia